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HM-65262/883
March 1997
16K x 1 Asynchronous CMOS Static RAM
Description
The HM-65262/883 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262/883 is available in both JEDEC Standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high board-level packing density. Gated inputs lower standby current, and also eliminate the need for pullup or pull-down resistors. The HM-65262/883, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max * Low Standby Current. . . . . . . . . . . . . . . . . . . . 50A Max * Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max * Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20A Max * TTL Compatible Inputs and Outputs * JEDEC Approved Pinout * No Clocks or Strobes Required * Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC * Gated Inputs-No Pull-Up or Pull-Down Resistors Required * Equal Cycle and Access Time * Single 5V Supply
Ordering Information
70ns/20A HM4-65262B/883 85ns/20A HM1-65262/883 HM4-65262/883 85ns/400A TEMP. RANGE -55oC to +125oC -55oC to +125oC PACKAGE CERDIP CLCC PKG. NO. F20.3 J20.C
Pinouts
HM1-65262/883 (CERDIP) TOP VIEW HM-65262 (CLCC) TOP VIEW
VCC A13 A1 A0
A0 A1 A2 A3 A4 A5 A6 Q W
1 2 3 4 5 6 7 8 9
20 VCC 19 A13 18 A12 17 A11 16 A10 15 A9 14 A8 13 A7 12 D 11 E A2 3 A3 4 A4 5 A5 6 A6 7 Q8
2
1 20 19 18 A12 17 A11 16 A10 15 A9 14 A8 13 A7
A0 - A13 E Q D VSS/GND VCC W
Address Input Chip Enable/Power Down Data Out Data In Ground Power (+5) Write Enable
9 10 11 12 GND W D E
GND 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3003.2
6-204
HM-65262/883 Functional Diagram
A0 A1 A2 A3 A4 A12 A13
A 7 ROW ROW ADDRESS DECODER 128 MEMORY ARRAY BUFFER A (1 OF 128) 128 X 128 7 128 COLUMN DECODER (1 OF 128) AND I / O CIRCUITRY A 7 A 7 Q
D
E COLUMN ADDRESS BUFFERS W
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A7 A8 A9 A10 A11 A5 A6
HM-65262/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades . . . . . -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JC Thermal Resistance (Typical) JA CERDIP Package . . . . . . . . . . . . . . . . . . 66oC/W 13oC/W 18oC/W CLCC Package. . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2V to VCC Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-65262/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested (NOTE 1) CONDITIONS VCC = 4.5V, IO = -4.0mA VCC = 4.5V, IO = 8.0mA VCC = 5.5V, E = 5.5V, VO = GND or VCC VCC = 5.5V, VI = GND or VCC VCC = 5.5V, IO = 0mA, E = VCC -0.3V VCC = 5.5V, IO = 0mA, E = 2.2V VCC = 5.5V, (Note 2), f = 1MHz, E = 0.8V VCC = 2.0V, IO = 0mA, E = VCC -0.3V VCC = 5.5V, IO = 0mA, E = 0.8V VCC = 4.5V (Note 3) GROUP A SUB-GROUPS 1, 2, 3 1, 2, 3 1, 2, 3
DC PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Standby Supply Current
SYMBOL VOH1 VOL IOZ
TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
MIN 2.4 -1.0
MAX 0.4 1.0
UNITS V V A A A
II ICCSB1
1, 2, 3 1, 2, 3
-1.0 -
1.0 50
Standby Supply Current Operating Supply Current Data Retention Supply Current Enable Supply Current Functional Test
ICCSB ICCOP
1, 2, 3 1, 2, 3
-
5 50
mA mA A
ICCDR
1, 2, 3
-
20
ICCEN FT
1, 2, 3 7, 8A, 8B
-
50 -
mA -
NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH 1.5V, and VOL 1.5V. TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
AC PARAMETER
Read/Write/Cycle Time Address Access Time
SYMBOL
(1) TAVAX
(NOTES 1, 2) CONDITIONS
VCC = 4.5V and 5.5V
GROUP A SUBGROUPS
9, 10, 11
HM65262B/883 LIMITS TEMPERATURE
-55oC TA +125oC -55oC TA +125oC
HM-65262/883 LIMITS MIN
85
MIN
70
MAX
-
MAX
-
UNITS
ns
(2) TAVQV
VCC = 4.5V and 5.5V
9, 10, 11
-
70
-
85
ns
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HM-65262/883
TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
AC PARAMETER
Chip Enable to End of Write Chip Enable Access Time Address Hold Time Address Setup Time Address Valid to End of Write Address Setup Time Address Hold Time Address Valid to End of Writes Write Enable Pulse Write Data Setup Time Data Hold Time Enable Pulse Width Write to End of Write Data Setup Time Data Hold Time
SYMBOL
(3) TELWH
(NOTES 1, 2) CONDITIONS
VCC = 4.5V and 5.5V
GROUP A SUBGROUPS
9, 10, 11
HM65262B/883 LIMITS TEMPERATURE
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
HM-65262/883 LIMITS MIN
65
MIN
55
MAX
-
MAX
-
UNITS
ns
(4) TELQV
VCC = 4.5V and 5.5V
9, 10, 11
-
70
-
85
ns
(5) TWHAX (6) TAVWL (7) TAVWH
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11 9, 10, 11
0 0 55
-
0 0 65
-
ns ns ns
(8) TAVEL (9) TEHAX (10) TAVEH
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11 9, 10, 11
0 0 55
-
0 0 65
-
ns ns ns
(11) TWLWH
VCC = 4.5V and 5.5V
9, 10, 11
40
-
45
-
ns
(12) TDVWH (13) TWHDX (14) TELEH (15) TWLEH
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
30 0 55 40
-
35 0 65 45
-
ns ns ns ns
(16) TDVEH (17) TEHDX
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11
30 0
-
35 0
-
ns ns
NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC
LIMITS PARAMETER Input Capacitance SYMBOL (NOTE 1) CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds Output Capacitance NOTES 1, 2 TEMPERATURE TA = +25oC MIN MAX 10 UNITS pF
CIN
1, 3
TA = +25oC
-
6
pF
CO
VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds
1, 2
TA = +25oC
-
12
pF
1, 3
TA = +25oC
-
8
pF
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HM-65262/883
TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC (Continued)
LIMITS PARAMETER Write Enable to Output in High Z SYMBOL (NOTE 1) CONDITIONS VCC = 4.5V and 5.5V NOTES 1 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oCMIN MAX 40 UNITS ns
(18) TWLQZ (19) TWHQX (20) TELQX (21) TEHQZ (22) TEHQX (23) TAXQX (24) VOH2
Write Enable High to Output ON
VCC = 4.5V and 5.5V
1
0
-
ns
Chip Enable to Output ON
VCC = 4.5V and 5.5V
1
5
-
ns
Output Enable High to Output in High Z Chip Disable to Output Hold Time
VCC = 4.5V and 5.5V
1
-
40
ns
VCC = 4.5V and 5.5V
1
5
-
ns
Address Invalid Output Hold Time
VCC = 4.5V and 5.5V
1
5
-
ns
High Level Output Voltage
VCC = 4.5V, IO = -100mA
1
VCC -0.4V
-
V
NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to DIP device types only. 3. Applies to LCC device types only. TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
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HM-65262/883 Timing Waveforms
A
(4) TELQV E (21) TEHQZ (20) TELQX (22) TEHQX Q
NOTE: 1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high. FIGURE 1. READ CYCLE 1: CONTROLLED BY E
(1) TAVAX
A (2) TAVQV E (20) TELQX (21) TEHQZ (23) TAXQX Q
NOTE: 1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid. FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS
(1) TAVAX A (7) TAVWH (3) TELWH E (6) TAVWL W (5) TWHAX
(21) TEHQZ (11) TWLWH
(12) TDVWH D (18) TWLQZ (20) TELQX Q
(13) TWHDX
(19) TWHQX
NOTE: 1. In this mode, E rises after W. The address must remain stable whenever both E and W are low. FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)
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HM-65262/883 Timing Waveforms
(Continued)
(1) TAVAX A (10) TAVEH (8) TAVEL E (14) TELEH (9) TEHAX
(15) TWLEH
W (19) TWHQX (16) TDVEH D (17) TEHDX
(20) TELQX Q (18) TWLQZ (21) TEHQZ
NOTE: 1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle. FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (E) must be held high during data retention; within VCC to VCC +0.3V. 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation >55ns after VCC reaches the minimum operating voltage (4.5V).
DATA RETENTION MODE VCC 4.5V VCC 2.0V 4.5V >55ns E VCC -0.3V TO VCC +0.3V
FIGURE 5. DATA RETENTION TIMING
6-210
HM-65262/883 Test Circuit
DUT (NOTE 1) CL
IOH
+ -
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: 1. Test head capacitance includes stray and jig capacitance.
Burn-In Circuits
HM-65262/883 CERDIP TOP VIEW HM-65262/883 CLCC TOP VIEW
VCC F16 F4 F0 A0 A1 A2 A3 A4 A5 A6 Q W GND VCC A13 A12 A11 A10 A9 A8 A7 D E F16 A1 F15 F14 F13 F12 F11 F10 F2 F0 F7 F8 F9 F2 Q A5 A6 7 8 9 W 10 GND 11 E 12 D A2 F5 A3 F6 A4 5 6 4 3 A0 C
F3 F4 F5 F6 F7 F8 F9 F2 F1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1 20
2
A13 19 A12 18 17 16 15 14 13 A11 A10 A9 A8 A7 F15 F14 F13 F12 F11 F10 F0 F2
NOTES: All resistors 47k 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F13 = F12 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C = 0.01F Min.
NOTES: All resistors 47k 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F13 = F12 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C = 0.01F Min.
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F1
HM-65262/883 Die Characteristics
DIE DIMENSIONS: 148 x 187 x 19 mils METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.2 x 105 A/cm2
Metallization Mask Layout
HM-65262/883
A2 A3 A4 A1 A0 VCC A13 A12 A11 A10
A5
A9 A8 Q W GND E D A7
A6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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